The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices. The present invention has particular applicability to double-gate devices.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In several respects, the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
A FinFET is a recent double-gate structure that exhibits good short channel behavior. Although conventional FinFETs are referred to as xe2x80x9cdouble-gatexe2x80x9d MOSFETs, the two gates typically are physically and electrically connected and thus form a single logically addressable gate. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the present invention provide a FinFET device with two gates that are effectively separated from each other by a conductive fin. The gates may be independently biased for increased circuit design flexibility.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device including a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of number of side surfaces of the fin. A second gate may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.
According to another aspect of the invention, a method of manufacturing a semiconductor device may include forming an insulating layer on a substrate and forming a fin structure on the insulating layer. The fin structure includes a first side surface, a second side surface, and a top surface. The method may also include forming source and drain regions at ends of the fin structure and depositing a gate material over the fin structure. The gate material surrounds the top surface and the first and second side surfaces. The gate material may be etched to form a first gate electrode and a second gate electrode on opposite sides of the fin. The deposited gate material may be planarized proximate to the fin.
According to a further aspect of the invention a semiconductor device may include a substrate and an insulating layer formed on the substrate. A conductive fin may be formed on the insulating layer, and gate dielectric layers may be formed on side surfaces of the conductive fin. A first gate electrode may be formed on the insulating layer. The first gate electrode may be disposed on a first side of the conductive fin adjacent to one of the gate dielectric layers. A second gate electrode may be formed on the insulating layer. The second gate electrode may be disposed on an opposite side of the conductive fin adjacent to another one of the gate dielectric layers and spaced apart from the first gate electrode.